In networking devices it is important to maintain accurate packet and byte counters for all traffic flowing through the devices. Such counters are important for customers, for lab testing, and also for verification and debugging purposes. Generally, counters must be maintained for a large number of items in a few different categories (e.g., individual routes the packets are taking, the adjacencies/next hops of the packets, etc.). It is not unusual for a network device to need to maintain counters on packets arriving at a rate of fifty million packets per second, and to have to support one million routes (i.e., one million different sets of packet and byte counters in the route category). Many communications and computer systems keep large numbers of counters to indicate that certain events have occurred. Examples of such events include packets forwarded, bytes forwarded, overrate bytes and underrate bytes. Externally-visible counters (i.e., those available to the system, which are typically accumulated values from the counter bank counters maintained inside components) typically must maintain total event counts that last for days, weeks, or even years.
In implementations with counters implemented on an application-specific integrated circuit (ASIC), it is not uncommon for the counter state to total many megabits of on-chip or custom off-chip memory occupying a non-trivial fraction of the total chip area. For example, one packet switch uses roughly 150,000 on-chip packet and byte counters with each counter having thirty-two bits of on-chip storage totaling 4.8 megabits of on-chip storage. Therefore, it is valuable if the on-chip storage required can be reduced while still ensuring that counters presented to the user do not wrap, and while not increasing CPU burden or bus bandwidth utilization required to read them periodically. An issue in maintaining these counters is providing the necessary combination of storage space and bandwidth in a fashion that is cost effective, low in power, and low in pin count. Complicating the bandwidth issue is that as the number of counters grows the frequency at which software can reasonably read an individual counter lessens. The size and number of counters make storing the full counters directly on a packet switching chip expensive with today's technologies.